With the development of wireless communications technologies, a mobile communications device generally needs to support multimode and multiband requirements, which requires that, on the mobile communications device, an antenna not only needs to support switching from a transmit mode to a receive mode, but also needs to meet the multimode and multiband requirements.
In a radio frequency apparatus, there are a transmit link and a receive link, and the transmit link and the receive link may be collectively called a radio frequency processing module. When the radio frequency processing module determines to perform at least one of signal sending and signal receiving, at least one of the transmit link and the receive link needs to be selectively connected to an antenna, where the selective connection is generally implemented by using a SPDT (Single-Pole Double-Throw, single-pole double-throw) switch, as shown in FIG. 1. A radio frequency processing module in FIG. 1 includes a transmit link and a receive link, and when the SPDT switch connects the antenna to the transmit link, the transmit link is configured to modulate a baseband signal to obtain a radio frequency signal, and the antenna is configured to send the radio frequency signal that is obtained after the modulation. When the SPDT switch connects the antenna to the receive link, the receive link is configured to demodulate a signal received by the antenna. In order to optimize antenna efficiency, a tuner, acting as an apparatus for adjusting antenna impedance matching, is introduced into the radio frequency apparatus. The tuner may be an impedance matching network that is connected between the radio frequency module and the antenna, and is capable of performing impedance matching processing on the antenna, so as to optimize transmit performance of the antenna. As shown in FIG. 1, the tuner may be coupled between the antenna and the SPDT switch. Optionally, the antenna tuner may also be coupled between the SPDT switch and the radio frequency module. The tuner generally includes switches, capacitors, a resistor, an inductor, or another component. A control signal is used to control turn-on or turn-off of multiple switches in the tuner, so as to change a connection relationship between capacitors in the tuner or between a capacitor and another component that are in the tuner, for example, a connection relationship between the inductor and the resistor, to tune a radio frequency signal to be input to the antenna, where the circuit formed by the switch and the capacitor is also called a digitally tunable capacitor (Digitally Tunable Capacitor, DTC). Therefore, performance of the switch in the tuner affects operation of the tuner to a large degree.
The switch in the tuner may be as shown in FIG. 2A. In order not to be broken down in a case in which a high-power control signal is borne, the switch in the tuner needs to apply a design in which multiple transistors are stacked, where stacking refers to serial connection of the multiple transistors. Illustration is provided in FIG. 2A by using an example, in which multiple MOS (Metal-Oxide-Semiconductor, metal-oxide-semiconductor) transistors are serially connected, the multiple serially connected MOS transistors act as a switch, and the switch has an input end configured to input a signal, an output end configured to output a signal, and a control end. The control end of the switch receives a control signal, and under control of the control signal, turns on or turns off the switch. When the switch is turned on, a signal input by the input end is transmitted to the output end; and when the switch is turned off, an input signal is not transmitted to the output end. A gate and a source of each MOS transistor have large parasitic capacitance, and therefore a high-power high-frequency control signal of the gate may be directly coupled to the source, that is, output of the MOS transistor is affected, so that resistance between the gate and the control signal needs to be increased for isolation; otherwise, a gate leakage current, that is, a current leaking from the gate, is fairly large, which causes a large signal loss, thereby deteriorating performance of the switch. In FIG. 2A, involved MOS transistors are all NMOS (N-Metal-Oxide-Semiconductor, N-metal-oxide-semiconductor) transistors, each of which is indicated by a mark M. A gate leakage current of each NMOS transistor is indicated by Ig. A schematic diagram of one NMOS transistor may be as shown in FIG. 2B, which includes a source S, a gate G, and a drain D. When the gate G is at a high voltage level, the NMOS transistor is on, the source S and the drain D are connected, and an input of the drain D is conducted to the source S; and when the gate G is at a low voltage level, the NMOS transistor is off, and a path from the drain D to the source S is blocked.
Definitely, when the switch is manufactured by using an integrated circuit process, other different types of transistors may also be used, for example, a PMOS (P-Metal-Oxide-Semiconductor, P-metal-oxide-semiconductor) transistor may also be used to replace the NMOS transistor. A schematic diagram of the PMOS transistor may be as shown in FIG. 2C. Different from that in an NMOS, in the PMOS transistor, when a gate G is at a high voltage level, an input path from a source S to a drain D is blocked; and when the gate G is at a low voltage level, an input of the source S is conducted to the drain D.
When an isolation resistor is added to a transistor to reduce a leakage current, according to the prior art, in multiple serially connected MOS transistors, a gate of each MOS transistor is connected to an isolation resistor to reduce the gate leakage current Ig, and an isolation resistor similar to that of the gate may also be added to a substrate of each transistor, so as to reduce a substrate leakage current. As shown in FIG. 3, multiple NMOS transistors M are serially connected, the gate and the substrate of each NMOS transistor may be both coupled to a gate control signal and a substrate control signal respectively through isolation resistors R, but these isolation resistors R are not directly connected to the gate control signal and the substrate control signal, and instead, these isolation resistors R are further connected to the gate control signal and the substrate control signal through one resistor r, so as to reduce the leakage current. However, the gate or the substrate of each transistor is connected to only two serially connected resistors R and r, so that a degree of isolation may not meet a requirement in some scenarios.
In order to further improve a degree of gate resistor isolation of the multiple serially connected MOS transistors, another prior art proposes a connection relationship between the MOS transistors and the resistors, as shown in FIG. 4. In a series of serially connected MOS transistors, each transistor is indicated by M, a gate of each MOS transistor and a gate of an MOS transistor adjacent to the MOS transistor are connected through a gate resistor R, and a gate resistor of the MOS transistor close to an output end is connected to one resistor r, so that a control signal is received through the resistor r, and therefore resistor isolation from the control signal to the transistor is improved. Because a quantity of serially connected resistors from the gate of a transistor close to an input end to a switch control end is increased, the degree of isolation is improved accordingly. However, for the transistor close to the input end, as a quantity of serially connected resistors that are coupled to the control end increases, a transmission delay of a signal from the control end to the gate of the transistor increases, so that transmission efficiency of the entire switch is reduced. Therefore, how an excessive loss of the transmission efficiency is to be avoided when a leakage current of a transistor is reduced becomes a problem.